1. Technical Field
The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
2. Related Art
A structure for a semiconductor device such as an IGBT is known in which the surface area of an emitter region connected to the emitter electrode is reduced by providing floating regions in the substrate surface on the emitter side, as shown in Patent Documents 1 and 2, for example. Furthermore, each floating region is separated from other regions by a gate trench, and channel layers or the like are formed between respective floating regions. For example, as shown in FIG. 9 of Patent Document 2, a gate electrode in a gate trench is connected to a wiring portion arranged outside of the floating regions.    Patent Document 1: Japanese Patent Application Publication No. 2007-324539    Patent Document 2: Japanese Patent Application Publication No. 2011-243946
The wiring portion is preferably capable of reliably connecting to the gate electrode. Furthermore, the channel layer or the like preferably has a shape allowing for easy formation of other structures.